Integrated circuits have progressed to advanced technologies with high packing densities and smaller feature sizes, such as 45 nm, 32 nm, 28 nm and 20 nm. In these advanced technologies, a planar field effect (or two dimensional) transistor has a channel configured in a top surface with a limited channel width. Thus, the capacitive coupling between the gate electrode and the channel is limited as well. When the feature size is reduced, the channel width cannot be reduced proportionally to retain or enhance the device performance. Accordingly, the transistor occupies more circuit area and the packing density is higher. There are trade off between the device performance and the packing density. Therefore, there is a need of a transistor structure and a method making the structure to address the above concerns.